1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device using standard cells and a manufacturing method of interconnection of the same, and particularly to a semiconductor integrated circuit device laid out or designed with CAD (computer aided design) and a wiring method of the same.
2. Description of the Related Art
In recent years, remarkable development of semiconductor techniques has realized integration of many functions and systems in one chip. Therefore, demands for the integration of various systems in one chip have been increased in various applications day by day. Further, users having such demands also wish to obtain integrated circuits having desired functions in a short time. However, manual design of circuits formed of hundreds of thousands transistors requires much time, and discovery of errors in the design also requires considerable time and costs. Therefore, demands for automatic design of the integrated circuits can be automatically carried out with computers as far as possible have currently occurred. CAD techniques have been developed for achieving the above demands, and particularly, automatic layout and interconnection programs using standard cells have been used for designing the semiconductor integrated circuit devices in the simplest manner. The automatic layout and interconnection program using the standard cells are disclosed, for example, in "Semi-Custom-IC Design and VESI", P. J. Hicks, 1983.
Here, the standard cells are used for a method in which standard circuit block cells previously designed and registered in a cell library are used for the design of the LSI's, and thus they are used in one of design methods for the semi-custom LSI's. This method is different from a gate array method which is also used for the semi-custom LSI's in that a mask is formed for every circuit.
FIG. 6 illustrates a general construction of a semi-custom LSI fabricated with an automatic layout and interconnection program using standard cells. Referring to FIG. 6, a semi-custom LSI 10 includes a group of standard cells 11 as well as a power supply line 8a and a ground line 8b for supplying a power supply line and a ground line to the standard cells 11.
FIG. 7 is an enlarged view of a part of the semi-custom LSI shown in FIG. 6. Referring to FIG. 7, the standard cell group 11a includes the standard cells 1a-1e. The standard cells 1a-1e are coupled to standard cells in another standard cell group 11b through signal lines 7a-7c and others, respectively.
Now, contents of the standard cells will be described with reference to FIGS. 8A-8C. FIG. 8A is a view for illustrating the contents in the standard cell 1a. FIGS. 8B and 8C are fragmentary cross sections taken along lines VIIIB--VIIIB and VIIIC--VIIIC in FIG. 8A. Referring to FIG. 8A, the standard cell 1a includes a plurality of longitudinally disposed I/O terminals 2a-2d, metal interconnections 5b and 5a for the ground line and the power supply line which are disposed at upper and lower edges (in FIG. 8A) of the standard cell to cross the I/O terminals 2a-2d, respectively, metal, interconnection layers 3a-3d for coupling the I/O terminals 2a-2d, and input pins 4b and 4a at a ground side and a power supply side for coupling the metal interconnections 5b and 5a for the ground line and for the power supply line to those in an adjacent standard cell, respectively.
The metal interconnection 5a for the ground line and the metal interconnection 5b for the power line are spaced from the metal interconnection layers 3a-3d with an insulator layer 21 therebetween, as shown in FIGS. 8B and 8C.
The standard cell 1a is a circuit which can achieve arbitrary logic such as logical sum, logical product or counting, and various types of circuits have been previously prepared.
As shown in FIG. 8A, an interconnection of a large width is usually used as the metal wiring 5a for the power supply, because a higher current will flow through the power supply line as compared with the general signal lines. Active elements such as transistors are formed in an active element forming region 6 which is located above the metal interconnection layers 3a-3d and between the metal interconnections 5a and 5b. The active elements such as transistors are coupled to the metal interconnection layers 3a-3d and to the metal interconnections 5a and 5b for the ground line and the power line, respectively, to form the standard cell having the intended logical function.
An example in which a logic circuit is formed using the standard cell will be described with reference to FIG. 7. The logic circuit, e.g., for the logical sum or logical product requires power supply signals to be supplied thereto. As already described with reference to FIG. 8A, the metal interconnection for the power supply is laterally disposed in the standard cell 1a. The standard cells 1a-1d are laterally aligned to each other so as to contact the input pins 4b at the ground line side together and to contact the input pins 4a at the power line side together, and the power supply line 8a and the ground line 8b are coupled to opposite sides of a row thus formed. In this manner, the standard cells each having a single logical function are combined to achieve an intended circuit operation in the whole semiconductor integrated circuit.
As shown in FIG. 7, the power supply line 8a and the ground line 8b located outside the standard cell row are usually formed of interconnecting having larger widths than general signal lines 7a-7c. An automatic layout and interconnection program enables automatic fabrication of a construction described above with a computer in a short time.
Meanwhile, the power signal is required to be coupled to the input signal in the logic circuit in some cases. These cases will be described with reference to FIG. 9. The power supply is an essential component in the logic circuit, and generally is not used for the signals. However, in the automatic layout and interconnection program using the standard cells, e.g., for the AND circuits, standardization of the standard cells is achieved by using those having even pins such as 6 pins or 8 pins as the input terminals, and those having odd terminals are not used for the purpose. In this case, if the AND circuit of 6 pins is used as the AND circuit of 5 pins, the remaining one terminal is coupled to the supply potential as shown in FIG. 9(b). In this manner, the AND circuit of 6 pins is used as the AND circuit of 5 pins, as shown in FIG. 9(a). In this case, this power signal is called as the power signal line so as to distinguish it from the power supply line. The automatic layout and interconnection program has conventionally achieved the usage of the power signal line in the standard cell in the following manner.
FIG. 10 illustrates a manner for coupling the power signal line to the standard cell 1c by the automatic layout and interconnection program of the prior art. Referring to FIG. 10, a power signal line 12 is coupled directly between the standard cell 1c and the power supply line 8a located outside a row of the standard cells. The power signal line 12 located between the standard cell 1c and the power supply line 8a located outside the cell row is long and thick. The power signal line 12 have the same configuration as a power coupling line 13a, so that it requires a large interconnecting width and an excessive area in a semi-custom LSI. Therefore, the power signal line 12 which is coupled to an input signal of the standard cell 1c must be reduced in width. It is, however, difficult to distinguish the power signal line 12 and the power coupling line 13a from each other by means of software, so that this method has not been used to a large extent.
FIG. 11 illustrates another example in which the power signals are applied to the standard cell 1c in the automatic layout and interconnection program of the prior art. Referring to FIG. 11, adjacent to the standard cell 1c which is to receive the power signals, there is disposed a special standard cell 9 for supplying the power signals, and the special standard cell 9 is coupled, by its output signal, to the input terminal of the standard. cell 1c which requires the power signals, whereby the power signals are applied thereto. FIG. 12 illustrates this special standard cell 9 in greater details. Referring to FIG. 12, the special standard cell 9 has a construction in which the power supply line 5a in the standard cell and the metal interconnection layer 3 are coupled together through a via hole or a through hole. That is; the metal interconnections of the different layers in the semiconductor integrated circuit are short-circuited in the special standard cell 9. Since the program handles the output of this special standard cell 9 similarly to the general signal lines, it is not necessary to give special attention to the wiring width. In this case, it is necessary to previously describe an item relating to this special standard cell 9 in a logical diagram. The automatic layout and interconnection program uses this logical diagram to achieve the layout and interconnection of the standard cells 1 and the special standard cell 9.
A specific example of the logic circuit using this standard cell 9 will be described below.
FIGS. 13A and 13B illustrate a specific layout of the standard cell in an AND circuit of 6 inputs in which the special standard cell 9 is used for coupling the power signal line. FIG. 13A is a circuit diagram, and FIG. 13B is a layout diagram of a practical standard cell corresponding to it. Referring to FIG. 13B, the special standard cell 9 is disposed adjacent the 6 input AND circuit A.
Meanwhile, the Japanese Patent Laying-Open No. 61-123153 and others have disclosed a construction of a gate array LSI device in which an input terminal of an output circuit having multiple input logical functions is clipped to a predetermined potential. FIG. 14 is a view disclosed in the above publication. Referring to FIG. 14, there are provided input terminals IN1, IN2 and IN3, and a polysilicon interconnection 20 for the clip which is disposed, for example, perpendicularly to the terminals and is coupled to an aluminum interconnection of a power supply V.sub.DD through a contact hole 25. If the wiring 20 for the clip is to be coupled to one of the input terminals IN1, IN2 and IN3, a contact hole 21 or the like is provided at an intersection therebetween.
If it is necessary to supply the power signals to the particular standard cell 1c, the conventional automatic layout and interconnection program achieves it in the following manner. In the automatic formation of the layout of the semiconductor integrated circuit by the automatic layout and interconnection program, and particularly when a signal line such as the power signal which exists commonly in the standard cells is coupled as the input signal in the standard cell, there have been large useless region formed. This results in a problem that these regions occupy a large area in the semiconductor integrated circuit.
Further, if the input terminal or others is to be clipped to the predetermined potential in the gate array LSI device, the interconnection for the clip is located outside the cell, which also results in a problem that useless regions increase in the semiconductor integrated circuit.